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INE/AUTC 10.0

A dual-path subsampling PLL with ring VCO phase noise suppression

This article presents a 2-GHz dual-path subsampling phase-locked loop (SSPLL) with ring voltage-controlled oscillator (VCO) phase noise suppression (PNS). In addition to the conventional subsampling charge pump (SSCP), a high pass path from the subsampling phase detector (SSPD) to the low-pass filter (LPF) is implemented in the proposed SSPLL. Due to this dual-path architecture, a new in-band zero and pole are introduced into the open-loop transfer function (zero frequency is smaller than the pole frequency), which extends the open-loop unit-gain bandwidth without sacrificing the phase margin. Consequently, the phase noise contribution of the ring VCO is suppressed while the loop stability is ensured. Meanwhile, the phase noise contribution of the high-pass path is negligible compared to the reference and ring VCO’s contribution. Measurement results show that the SSPLL’s closed-loop bandwidth is extended to around 6 MHz with a reference of 20 MHz and the jitter is reduced by 1.34× (from 3.52 to 2.63 ps) with a maximum noise suppression of 6.5 dB at the 1.1-MHz offset. The PNS path consumes 0.16 mW and no delay line or calibration is needed, which results in a relatively high FoMPNC value of 40.5 dB.Info-communications Media Development Authority (IMDA)National Research Foundation (NRF)Submitted/Accepted versionThis work was supported in part by the National Research Foundation, Singapore; and in part by the Infocomm Media Development Authority under its Future Communications Research and Development Program

A low-power quadrature LO generator with mutual power-supply rejection technique

This paper presents a supply-insensitive low-power quadrature local oscillation (LO) generator based on the current-reused voltage-controlled oscillator (VCO) and divide-by-two frequency divider (FD). By utilizing the mutual power-supply rejection (M-PSR) technique, a voltage regulator is embedded into the FD to provide a supply-insensitive voltage for VCO. Meanwhile, the feedback loop provides a supply-insensitive current and time constant compensation for FD. The M-PSR technique does not require extra voltage headroom, thus the proposed quadrature LO generator can work under the supply of 0.9 V. A prototype of the proposed quadrature LO generator is implemented in a 28-nm CMOS process. Measurement results indicate that the LO generator achieves a phase noise of -110.5 dBc/Hz@1MHz at the carrier of 5.9 GHz and the power consumption is 1.8 mW. This work has a competitive figure of merit in supply sensitivity or in area (FOMss or FOMa respectively) among the state-of-the-art works.Ministry of Education (MOE)Published versionThis work was supported in part by Singapore Ministry of Education Academic Research Fund Tier 2 under Grant MOE2019-T2-1-114, and in part by China Scholarship Council

A wideband variable-gain amplifier with a negative exponential generation in 40-nm CMOS technology

A wideband variable-gain amplifier (VGA) with a negative exponential generation using 40 nm CMOS technology is reported. By compensating a single-branch negative exponential generator (NEG) which features a composite of dual Taylor series, the proposed negative exponential generation further extends the dB-linear range. The measurement results show the overall VGA achieves a dB-linear range of 51 dB (-34 ~ 17dB) with a gain error less than ± 1 dB. In addition, the bandwidth is around 7 GHz under different gain settings. The core circuit draws 24.6 mA current from a 1.1 V power supply (excluding the output buffer) and occupies an active area of 0.038 mm2.Agency for Science, Technology and Research (A*STAR)Accepted versionThis research is supported by A*STAR under its RIE2020 Advanced Manufacturing and Engineering (AME) Industry Alignment Fund - Pre Positioning (IAF-PP) (Award A19D6a0053)